Friday, May 27, 2011

Declaring Virtual Pins in Quartus

When the system design in FPGA gets bigger, then its much easier to break the jumbo block into sub-blocks and work on each of them. Upon testing (simulating) and synthesizing these sub-blocks independently, we can integrate these to get the final jumbo design block. This breaking and developing act makes the development easier and more error proof. Also, we can decrease the development time by handing over the sub-block design and verification to different individuals.

But, with the advantages, the breaking up of block into sub-blocks has few hurdles too. One of the significant hurdle is the increment in number of pins in the sub-blocks as compared to that of the final design. And we know that the number of pins supported by an FPGA is fixed.

Let us take an example :-
Suppose you have a Altera Stratix 4 device with 560 user I/O pins. Let us suppose the final design uses 540 I/O pins. And suppose you have divided the final design into sub-blocks A and B. Let us also suppose that "A" has 300 I/O pins usability and the "B" uses 600 I/O pins.

So, simulating and synthesizing the sub-block "A" may not be a hurdle. But when it comes to "B", you will face problem synthesizing the model because the number of pins is more than the pins supported by the FPGA. This is when Declaration of virtual pins come into our advantage.

Declaring the 60 or more pins in the design "B" will make sure that the design is synthesized by the Quartus tool.

Following are the steps to declare the virtual pins in Quartus:-
* We assume that the project is already opened in the Quartus tool. i.e. for Altera FPGA development.

Step 1:- Goto Assignments menu at the top of the window. Then select the Assignment Editor.
This will give you the Assignment Editor window as shown in the right hand side of
the image below.

Step 2:- Click on the "new" option as shown in the image below.

Step 3:- You will now get an editable row in the Assignment Editor. Make sure that the Category
menu at the right hand top of the editor, All is selected. Then, in the editable row,
Select Assignment Name as "Virtual Pin" and Value as "On". Now double click on the
To option of the editable row. You will then get a small icon for Node Finder as shown
in the image below. Click on it.

Step 4:- In the Node Finder window, you will see two big boxes with few options. Click on the
List option to get all the I/O pins being used in the sub-design in the left box.
Select the pins which you want to declare as virtual pins. Move this to the right hand
box. It will look something like the image below.

Step 5:- Then click on OK. The Assignment Editor will show the various virtual pins which you
declared. Once done with the checking, run the Analysis and Synthesis for the Project.
Verify the virtual pins declaration by checking the Analysis and Synthesis Report,
which will report the number of virtual pins used.

This technique of using virtual pins enables us to verify the designs of sub-blocks where the number of used pins is more than the pins available in the FPGA.

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